This invention relates generally to planarization of substrates and more particularly to chemical mechanical polish of metal substrates.
Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductive, semiconductive or insulative layers. After a layer is deposited, the layer is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e., the exposed surface of the substrate, becomes increasingly non-planar. This non-planar outer surface presents a problem for the integrated circuit manufacturer. Therefore, there is a need to periodically planarize the substrate surface to provide a relatively flat surface. In some fabrication processes, planarization of the outer layer should not expose underlying layers.
Chemical mechanical polishing (CMP) is one method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a polishing pad. The polishing pad may be either a xe2x80x9cstandardxe2x80x9d pad or a fixed-abrasive pad. A fixed-abrasive pad has abrasive particles held in a containment media, whereas a standard pad has a durable surface, without embedded abrasive particles. The carrier head provides a controllable load, i.e., pressure, on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles if a standard pad is used, is supplied to the surface of the polishing pad.
An effective CMP process not only provides a high polishing rate, but also provides a substrate surface which is finished and flat. The polishing rate, finish and flatness are determined by the pad and slurry combination, the relative speed between the substrate and pad, and the force pressing the substrate against the pad.
In applying conventional planarization techniques, such as CMP, it is extremely difficult to achieve a high degree of surface planarity. The metal features on the substrate are typically formed in an interlayer dielectric, such as silicon oxide layer, by a damascene technique wherein trenches are initially formed. A barrier layer, such as a tantalum-containing layer e.g. Ta, TaN, or alternatively titanium (Ti or TiN), is then deposited lining the trenches and on the upper surface of the silicon oxide interlayer dielectric. Copper or a copper alloy is then deposited, as by electroplating, electroless plating, physical vapor deposition (PVD) at a temperature of about 50xc2x0 C. to about 150xc2x0 C. or chemical vapor deposition (CVD) at a temperature under about 200xc2x0 C., typically at a thickness of about 8000 xc3x85 to about 18,000 xc3x85. The deposited copper is chemically oxidized and then removed using CMP to create features on the metal substrate.
In planarizing the wafer surface after copper metallization using CMP, undesirable erosion and dishing typically occur, decreasing the degree of surface planarity and challenging the depth of focus limitations of conventional photolithographic techniques, particular with respect to achieving submicron dimensions, such as about 0.25 micron. In addition, dishing reduces the size of circuit lines thereby increasing resistivity. Erosion is defined as the height differential between the oxide in the open field and the height of the oxide within the circuit array. Dishing is defined as a difference in height between the oxide and Cu in a feature (i.e. in a line or pad).
Dishing is caused, in general, by differences in hardness and chemical interaction across a surface. The mechanical and chemical interactions between the polishing pad and slurry and copper are different from the mechanical and chemical interactions between the polishing pad and slurry and oxide.
One of the causes of increased dishing arises from the difference in electrochemical potential between copper and barrier layer material. As the copper removal process approaches the copper/barrier interface, the substrate surface has both copper areas and barrier areas. An electrochemical effect takes place at the copper/barrier interface because of the electrochemical potential differential. The effect causes enhanced removal of copper in surface features and therefore causes higher dishing.
A second cause of increased dishing is the chemical loading effect. As the amount of copper is cleared from the surface, the ratio of polishing chemical in the slurry to copper on the substrate increases. This change in the chemical equilibrium of the CMP process in turn, enhances copper removal at surface features on the substrate.
It remains desirable to have a process of planarization where dishing is decreased.
It is an advantage of the present invention to provide a method and apparatus for substrate planarization producing a good quality substrate surface.
The problems of reducing dishing while achieving planarized processed substrates are solved by the present invention of a polish pad embedded with metal material having reductive properties for chemical mechanical polish.
Dishing in chemical mechanical polishing (CMP) is reduced by introducing a material that balances electrochemical forces. In a first embodiment of the invention, a polishing pad having copper material in grooves on the polishing pad surface is used in the polishing process to reduce dishing. In a second embodiment of the invention, the polishing pad has perforations with copper fillings. In a third embodiment of the invention, a copper retaining ring on the polishing head introduces copper material to the CMP process to reduce dishing. In a fourth embodiment of the invention, a conditioning plate of copper is used in the polishing apparatus. In a fifth embodiment of the invention, additional copper features are placed on the substrate to be polished. The polishing of the additional features introduces copper steadily through the polishing process. In a sixth embodiment of the invention, copper compounds are added to the polish slurry.